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1 dual 3a current sharing 2.5mhz high efficiency synchronous buck regulator isl78236 the isl78236 is a dual output 3a/3a integrated fet buck regulator for point-of-load power applications. the supply voltage range is from 2.8v to 6v, allowing for the use of a single li+ cell, three nimh cells or a regulated 3v/5v bus input. it is optimized for regula ting output voltages down to 1.2v. each channel provides an output current up to 3a which can be combined to form a single 6a output in current sharing mode. the two channels operate 180 out-of-phase to reduce input rms current and emi. the isl78236 integrates a pair of low on-resistance p-channel and n-channel internal mosfets to maximize efficiency and minimize external component count. it can operate up to 100% duty cycle to maximize operating life as battery voltage drops out. when supplying 3a on each channel, the 100% duty cycle operation limits the dropout voltage to less than 250mv. other features include internal digital soft-start, independent channel enable for power sequen cing, overcurrent protection, and thermal shutdown. the isl78236 is offered in a 24 ld 4mmx4mm qfn package with 1mm maximum height. the complete converter occupies less than 1.5cm 2 area. the isl78236 is aec - q100 qualified and is rated for the automotive temperature range (-40c to +105c). features ? dual 3a/3a independent outputs ? 2.5mhz synchronous buck regulator with internal mosfets up to 95% efficiency ? 2% voltage reference accuracy over-temperature ? 6a current sharin g mode operation ? internal or external compensation ? peak current limiting and hiccup mode short circuit protection ? reverse overcurrent protection ? over-temperature protection shutdown ? aec - q100 qualified applications ? dsp and embedded processor power supply ? infotainment system power ? automotive point of load power related literature ? an1927 , ?isl78236dualeval1z dual 3a low quiescent current high efficiency synchronous buck regulator? ? an1928 , ?ISL78236CRSHEVAL1Z current sharing 6a low quiescent current high efficiency synchronous buck regulator? figure 1. typical application block diagram: dual output 3a/3a buck regulator figure 2. efficiency vs load current, v in = 3.3v , t a = +25c isl78236 3v input en1 pg1 1.2v/3a 1.5v/3a fpga or dsp power asic power lx1 lx2 en2 pg2 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 output load (a) 2.5v out 1.2v out 1.8v out 1.5v out efficiency (%) caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2014. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. april 28, 2014 fn8624.0
isl78236 2 fn8624.0 april 28, 2014 submit document feedback table of contents typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 typical operating performance for dual pwm operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 typical performance for current sharing pwm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 theory of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 pwm control scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 synchronization control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 output current sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 power-good (pg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 uvlo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 soft start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 discharge mode (soft-stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 power mosfets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 100% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 output inductor and capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 minimum output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 loop compensation design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 pcb layout recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 thermal performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
isl78236 3 fn8624.0 april 28, 2014 submit document feedback typical applications figure 3. typical application diagram - single 6a figure 4. typical application diagram - dual 3a outputs l1 0.6h lx1 pgnd fb1 vin1, 2 en1 pg1 sync input 2.8v to 5v output 1.8v/6a c1 2x22f isl78236 r2 124k r3 100k vdd sgnd c3 12pf l2 0.6h fb2 c2 r6 50k 4x22f c6 150pf lx2 pgnd sgnd en2 pg2 comp ss c5 22nf to fb1 l1 0.6h lx1 pgnd fb1 vin en1 pg1 syn c input 2.8v to 5v output1 1.8v/3a c1 2x22f isl78236 c2 r2 124k r3 100k 2x22f vdd sgnd c3 12pf l2 0.6h fb2 output2 1.8v/3a c4 r5 124k r6 100k 2x22f c5 12pf lx2 pgnd sgnd en2 pg2 comp ss
isl78236 4 fn8624.0 april 28, 2014 submit document feedback table 1. component value selection for dual output operation v out 1.2v 1.5v 1.8v 2.5v 3.3v c1 2x22f 2x22f 2x22f 2x22f 2x22f c2 4x22f 4x22f 4x22f 4x22f 4x22f l1 (or l2) 0.5~1.1h 0.5~1.1h 0.5~1.68h 0.5~1.68h 0.5~2.2h r2 (or r5) 50k 87.5k 124k 212.5k 312.5k r3 (or r6) 100k 100k 100k 100k 100k table 2. component value selection for current sharing operation v out 1.2v 1.5v 1.8v 2.5v 3.3v c1 2x22f 2x22f 2x22f 2x22f 2x22f c2 (or c4) 2x22f 2x22f 2x22f 2x22f 2x22f l1 (or l2) 0.5~1.1h 0.5~1.1h 0.5~1.68h 0.5~1.68h 0.5~2.2h r2 50k 87.5k 124k 212.5k 312.5k r3 100k 100k 100k 100k 100k r6 33k 31k 30k 29k 28k c6 180pf 150pf 150pf 150pf 150pf
isl78236 5 fn8624.0 april 28, 2014 submit document feedback block diagram lx1 + + csa1 + + + slope comp star t soft- start 0.8v eamp pwm comp pwm logic controller protection driver fb1 + 0.736v 0.864v pg1 sync shutdown vin1 pgnd oscillator + bandgap scp + 0.5v en1 shutdown 1ms delay 0.3pf 27pf 390k sgnd 3pf 1.6k lx2 + + csa2 + + + slope comp star t soft- start 0.8v eamp comp pwm logic controller protection driver fb2 + 0.736v 0.864v pg2 shutdown vin2 pgnd + bandgap scp + 0.5v en2 shutdown 1ms delay sgnd 3pf 1.6k 1m thermal shutdown shutdown comp vin2 1m vin1 ocp threshold logic ss ss 0.3pf 27pf 390k
isl78236 6 fn8624.0 april 28, 2014 submit document feedback pin configuration isl78236 (24 ld qfn) top view lx2 pgnd2 pgnd2 pgnd1 pgnd1 lx1 comp nc fb1 sgnd pg1 sync lx2 vin2 vin2 en2 pg2 fb2 lx1 vin1 vin1 vdd ss en1 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 789101112 25 pad pin descriptions pin number symbol description 1, 24 lx2 switching node connection for channel 2. 4 en2 regulator channel 2 enable pin. enable the output, vout2, when driven to high. shutdown vout2 and discharge output capacitor when driven to low. do not leave this pin floating. 5 pg2 active high power-good (pg) indicator for channel 2. after power-up or en2 high, this output is a 1ms delayed power-good signal for the channel 2 output voltage. 6 fb2 the feedback network of the channel 2 regulator. fb2 is the negative input to the tran sconductance error amplifier. the output voltage is set by an external resistor divide r from vout2 connected to fb2. the power-good output and undervoltage lockout protection circuitry uses fb2 to monitor the channel 1 regulator output voltage. 7 comp comp pin is treated as a no connect in dual output mode operation, using only the internal compensation. if the ss pin is tied to a soft-start capacitor, exte rnal compensation is automatically used. an additional external network across comp and sgnd is required to improve the loop compensation of the amplifier in parallel current sharing operation. connect an external rc network on co mp pin for parallel mode operation. 8 nc no connect pin; please tie to gnd for thermal relief. 9 fb1 the feedback network of the channel 1 regulator. fb1 is the negative input to the tran sconductance error amplifier. the output voltage is set by an external resistor divide r from vout1 connected to fb1. the power-good output and undervoltage lockout protection circuitry uses fb1 to monitor the channel 1 regulator output voltage. 10 sgnd system ground. 11 pg1 active high power-good (pg) indicator for channel 1. after power-up or en1 high, this output is a 1ms delayed power-good signal for the channel 1 output voltage. 12 sync connect to logic high or input voltage vin. connect to an external function generator for external synchronization. negative edge trigger. do not leave this pin floating. do not tie this pin low (or to sgnd). 13 en1 regulator channel 1 enable pin. enable the output, vout 1, when driven to high. sh ut down vout1 and discharge output capacitor when driven to low. do not leave this pin floating.
isl78236 7 fn8624.0 april 28, 2014 submit document feedback 14 ss ss is used to adjust the soft-start time. when ss pin is tied to vin, ss time is 1.5ms. ss pin is tied to vin only in dual output mode operation. ss pin is tied to a soft-start capacitor only in parallel current sharing mode operation. connect a capacitor from ss to sgnd to adjust the soft-start time. c ss should not be larger than 33nf. this capacitor, along with an internal 5a current source, sets the soft-start interval of the converter, t ss . 15 vdd input supply voltage for the logic. vdd to be at the same potential as v in +0.3/-0.5v. 16, 17 2, 3 vin1, vin2 input supply voltage. connect 22f cerami c capacitor to power ground per channel. 18, 19 lx1 switching node connection for channel 1. 20, 21 pgnd1 negative supply for the power stage of channel 1. 22, 23 pgnd2 negative supply for the power stage of channel 2. 25 pad the exposed pad must be connected to the sgnd pin for pr oper electrical performance. a dd as many vias as possible to connect the pad to a ground plane for optimal thermal performance. pin descriptions (continued) pin number symbol description c ss ? f ?? 6.25 t ss s ?? ? = (eq. 1) ordering information part number ( notes 1 , 2 , 3 ) part marking temp. range (c) package (pb-free) pkg. dwg. # isl78236arz 782 36arz -40 to +105 24 ld 4x4 qfn l24.4x4d isl78236dualeval1z evaluation board ISL78236CRSHEVAL1Z evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ specia l pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compat ible with both snpb and pb-free soldering operations). intersi l pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see product information page for isl78236 . for more information on msl, please see tech brief tb363 .
isl78236 8 fn8624.0 april 28, 2014 submit document feedback absolute maximum ratings (reference to sgnd) thermal information vin1, vin2, vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v lx1, lx2 ( note 4 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v en1, en2, pg1, pg2, sync, ss. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v fb1, fb2, comp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +2.7v esd ratings human body model (tested per aec-q100-002) . . . . . . . . . . . . . . . . 4kv machine model (tested per aec-a100-003) . . . . . . . . . . . . . . . . . . . 300v charged device model (tested per aec-q100-011). . . . . . . . . . . . . . 2kv latch up (per jesd-78d; class 2, level a; aec-q100-004) . . . . . . 100ma thermal resistance (typical) ? ja (c/w) ? jc (c/w) 24 ld 4x4 qfn ( notes 5 , 6 ). . . . . . . . . . . 36 2 junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-55c to +150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c ambient temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +105c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions vin supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.85v to +6v load current range per channel . . . . . . . . . . . . . . . . . . . . . . . . . . . 0a to 3a ambient temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +105c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. values shown for continuous voltage. absolute maximum rating of 7v for a duration less than 20ms. absolute maximum rating of -1.5v for duration of less than 100ns. 5. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 6. for ? jc , ?case temperature? location is at the center of the exposed metal pad on the package underside. electrical specifications unless otherwise noted, the typical specificatio ns are measured at th e following conditions: t a = -40c to +105c, v in = 3.6v, en1 = en2 = vdd, l = 1.5h, c1 = c2 = c4 = 2x22f, i out1 = i out2 = 0a to 3a, unless otherwise noted. typical values are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +105c. parameter symbol test conditions min ( note 7 )typ max ( note 7 )units input supply vin undervoltage lockout threshold v uvlo rising 2.5 2.85 v hysteresis 40 100 mv quiescent supply current i vdd sync = v dd , en1 = en2 = vdd, no load at the output 30 70 ma shutdown supply current i sd v in = v dd = 6v, en1 = en2 = sgnd 8 35 a output regulation fb1, fb2 regulation voltage v fb 0.784 0.8 0.810 v fb1, fb2 bias current i fb vfb = 0.75v 1 a load regulation sync = vdd, output load from 0a to 6a 2 mv/a line regulation v in = v o + 0.5v to 6v (minimal 2.85v) 0.1 %/v soft-start ramp time cycle ss = vdd 1.5 ms soft-start charging current i ss 4 5 6 a compensation error amplifier trans-conductance ss = vdd 20 a/v ss with capacitor 100 a/v current sense amplifier gain csa_gain 0.172 0.2 0.228 v/a ch1/ch2 amplifier gain matching gain match -0.05 +0.05 v/a overcurrent protection dynamic current limit on-time t ocon 17 clock pulses dynamic current limit off-time t ocoff 8 ss cycle positive peak overcurrent limit i poc1 4.1 4.8 5.5 a i poc2 4.1 4.8 5.5 a negative peak overcurrent limit i noc1 -3.5 -2.5 -1.5 a i noc2 -3.5 -2.5 -1.5 a
isl78236 9 fn8624.0 april 28, 2014 submit document feedback lx1, lx2 p-channel mosfet on-resistance v in = 5.5v, i o = 200ma 50 75 m v in = 2.85v, i o = 200ma 70 100 m n-channel mosfet on-resistance v in = 5.5v, i o = 200ma 50 75 m v in = 2.85v, i o = 200ma 70 100 m lx_ maximum duty cycle 100 % pwm switching frequency f s 2.15 2.5 2.85 mhz synchronization frequency range f sync ( note 8 ) 68 mhz channel 1 to channel 2 phase shift ris ing edge to rising edge timing 180 lx minimum on time sync = high (pwm mode) 140 ns soft discharge resistance r dis en = low 80 100 120 lx leakage current v in = v dd = 6v 0.1 1 a pg1, pg2 output low voltage sinking 1ma, vfb = 0.7v 0.3 v pg pin leakage current pg = v in = 6v 0.01 0.1 a internal pgood low rising threshold percentage of nominal regulation voltage 88 92 95 % internal pgood low falling threshold percentage of nominal regulation voltage 85 88 92 % delay time (rising edge) time from vout_ reached regulation 1 ms internal pgood delay time (falling edge) 7 15 s en1, en2, sync logic input low 0.4 v logic input high 1.5 v sync logic input leakage current i sync v in = v dd = 6v 0.1 1 a enable logic input leakage current i en v in = v dd = 6v 0.1 1 a thermal shutdown 150 c thermal shutdown hysteresis 25 c notes: 7. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. 8. the operational frequency per switching ch annel will be half of the sync frequency. electrical specifications unless otherwise noted, the typical specificatio ns are measured at th e following conditions: t a = -40c to +105c, v in = 3.6v, en1 = en2 = vdd, l = 1.5h, c1 = c2 = c4 = 2x22f, i out1 = i out2 = 0a to 3a, unless otherwise noted. typical values are at t a = +25c. boldface limits apply across the operating te mperature range, -40c to +105c. (continued) parameter symbol test conditions min ( note 7 )typ max ( note 7 )units
isl78236 10 fn8624.0 april 28, 2014 submit document feedback typical operating performance for dual pwm operation unless otherwise noted, operating conditions are: t a = +25c; v out1 = 1.8v; v out2 = 1.8v; i out1 = 0a to 3a; i out2 = 0a to 3a, l1 = l2 = 0.6h, c out1 =2x22f, c out2 =2x22f, f sw = 2.5mhz. figure 5. efficiency, v in =3.3v, t a = +25c figure 6. efficiency, v in = 5v , t a = +25c figure 7. power dissipation, v in = 3.3v, v out = 1.8v figure 8. power dissipation, v in = 5v, v out = 1.8v figure 9. line regulation, v out = 1.8v, t a = +25c figure 10. load regulation, v out = 1.8v, t a = +25c 40 50 60 70 80 90 100 0 0.5 1.0 1.5 2.0 2.5 3.0 output load (a) efficiency (%) 2.5v out 1.2v out 1.8v out 1.5v out 40 50 60 70 80 90 100 0 0.5 1.0 1.5 2.0 2.5 3.0 output load (a) efficiency (%) 3.3v out 2.5v out 1.8v out output load (a) power dissipation (w) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 0.5 1.0 1.5 2.0 2.5 3.0 t = +125c t = -40c t = +105c t = +25c 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 0.5 1.0 1.5 2.0 2.5 3.0 output load (a) power dissipation (w) t = +125c t = -40c t = +105c t = +25c -0.05 0.00 0.05 0.10 0.15 0.20 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ? v out (%) input voltage (v) ? v out referenced from v out at v in = 2.7v 6a load 3a load 0a load -7 -6 -5 -4 -3 -2 -1 0 0 0.5 1.0 1.5 2.0 2.5 3.0 ? v out (mv) output current (a) ? v out referenced from v out at i out = 0a 3.3v in 5v in
isl78236 11 fn8624.0 april 28, 2014 submit document feedback figure 11. steady state operation at no load channel 1 figure 12. steady state operation at no load channel 2 figure 13. steady state operation at 3a load channel 1 figure 14. steady state operation at 3a load channel 2 figure 15. load transient channel 1 figure 16. load transient channel 2 typical operating performance for dual pwm operation unless otherwise noted, operating conditions are: t a = +25c; v out1 = 1.8v; v out2 = 1.8v; i out1 = 0a to 3a; i out2 = 0a to 3a, l1 = l2 = 0.6h, c out1 =2x22f, c out2 =2x22f, f sw = 2.5mhz. (continued) lx1 2v/div 200ns/div v out ripple 20mv/div il1 2a/div v in = 5v lx2 2v/div 200ns/div il2 2a/div v out ripple 20mv/div v in = 5v lx1 2v/div v out ripple 20mv/div il1 2a/div 200ns/div v in = 5v lx2 2v/div v out ripple 20mv/div il2 2a/div 200ns/div v in = 5v il1 2a/div v out1 ripple 100mv/div 100s/div ch2 i out = 0a v in = 5v il2 2a/div 100s/div ch1 i out = 0a v in = 5v v out2 ripple 100mv/div
isl78236 12 fn8624.0 april 28, 2014 submit document feedback figure 17. soft-start with no load channel 1 figure 18. soft-start with no load channel 2 figure 19. soft-start at 3a load channel 1 figure 20. soft-start at 3a load channel 2 figure 21. soft-discharge shutdown channel 1 figure 22. soft-discharge shutdown channel 2 typical operating performance for dual pwm operation unless otherwise noted, operating conditions are: t a = +25c; v out1 = 1.8v; v out2 = 1.8v; i out1 = 0a to 3a; i out2 = 0a to 3a, l1 = l2 = 0.6h, c out1 =2x22f, c out2 =2x22f, f sw = 2.5mhz. (continued) en1 v out lx1 voltage v in = 3.3v pg1 en2 v out lx2 voltage v in = 3.3v pg2 en1 v out lx1 voltage v in = 3.3v pg1 en2 v out lx2 voltage v in = 3.3v pg2 en1 v out lx1 voltage v in = 3.3v pg1 en2 v out lx2 voltage v in = 3.3v pg2
isl78236 13 fn8624.0 april 28, 2014 submit document feedback figure 23. steady state operation channel 1 at no load with f sw = 4mhz figure 24. steady state operation channel 2 at no load with f sw = 4mhz figure 25. steady state operation channel1 3a load with f sw = 4mhz figure 26. steady state operation channel2 3a load with f sw = 4mhz figure 27. output short circuit channel 1 figure 28. output short circuit recovery (from hiccup) channel 1 typical operating performance for dual pwm operation unless otherwise noted, operating conditions are: t a = +25c; v out1 = 1.8v; v out2 = 1.8v; i out1 = 0a to 3a; i out2 = 0a to 3a, l1 = l2 = 0.6h, c out1 =2x22f, c out2 =2x22f, f sw = 2.5mhz. (continued) sync lx1 2v/div 200ns/div v out1 ripple 50mv/div v in = 5v sync lx2 2v/div 200ns/div v out2 ripple 50mv/div v in = 5v sync lx1 2v/div 200ns/div, v out1 ripple 50mv/div out1 2a/div v in = 5v sync lx2 2v/div 200ns/div, v out2 ripple 50mv/div out2 2a/div v in = 5v lx1 5v/div il1 1a/div pg1 5v/div v out1 1v/div v in = 5v lx1 5v/div il1 1a/div pg1 5v/div v out1 1v/div v in = 5v
isl78236 14 fn8624.0 april 28, 2014 submit document feedback figure 29. output short circuit channel 2 figure 30. output short circuit recovery (from hiccup) channel 2 figure 31. lx jitter at no load, v in = 3v figure 32. lx jitter at 3a load, v in = 3v figure 33. lx jitter at no load, v in = 5v figure 34. lx jitter at 3a load, v in = 5v typical operating performance for dual pwm operation unless otherwise noted, operating conditions are: t a = +25c; v out1 = 1.8v; v out2 = 1.8v; i out1 = 0a to 3a; i out2 = 0a to 3a, l1 = l2 = 0.6h, c out1 =2x22f, c out2 =2x22f, f sw = 2.5mhz. (continued) lx2 5v/div il2 1a/div pg2 5v/div vout2 0.5v/div v in = 5v lx2 5v/div il2 1a/div pg2 5v/div vout2 1v/div v in = 5v 4ns/div 1v/div 4ns/div 1v/div 4ns/div 1v/div 4ns/div 1v/div
isl78236 15 fn8624.0 april 28, 2014 submit document feedback typical performance for current sharing pwm operation unless otherwise noted, operating conditions are: t a = +25c; v out = 1.8v, i out1 +i out2 = 0a to 6a, l1 = l2 = 0.6h, c out = 4x22f, f sw = 2.5mhz. figure 35. efficiency vs load, v in =3.3v, t a = +25c figure 36. efficiency vs load, v in =5v, t a = +25c figure 37. power dissipation, v in = 3.3v, v out = 1.8v figure 38. power dissipation, v in = 5v, v out = 1.8v figure 39. line regulation, v out = 1.8v, t a = +25c figure 40. load regulation, v out = 1.8v, t a = +25c 0123456 output load (a) 40 50 60 70 80 90 100 efficiency (%) 1.8 v out 1.2 v out 1.5 v out 2.5v out 40 50 60 70 80 90 100 0123456 output load (a) efficiency (%) 1.8v out 2.5v out 3.3v out output load (a) power dissipation (w) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 1 2 3 4 5 6 t = +125c t = -40c t = +105c t = +25c 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 1 2 3 4 5 6 output load (a) power dissipation (w) t = +125c t = -40c t = +105c t = +25c 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ? v out (%) input voltage (v) ? vout referenced from v out at v in = 2.7v 6a load 0a load 3a load -7 -6 -5 -4 -3 -2 -1 0 0 1 2 3 4 5 6 output current (a) -8 ? v out (mv) ? v out referenced from v out at i out = 0a 3.3v in 5v in
isl78236 16 fn8624.0 april 28, 2014 submit document feedback figure 41. steady state operation at no load figure 42. steady state operation at 6a load figure 43. load transient response figure 44. soft-discharge shutdown figure 45. soft-start at no load figure 46. soft-start at 6a load typical performance for current sharing pwm operation unless otherwise noted, operating conditions are: t a = +25c; v out = 1.8v, i out1 +i out2 = 0a to 6a, l1 = l2 = 0.6h, c out = 4x22f, f sw = 2.5mhz. lx1 5v/div v out ripple 100mv/div lx2 5v/div 200ns/div v in = 5v lx1 5v/div v out ripple 50mv/div lx2 5v/div 200ns/div v in = 5v v out ripple 200mv/div output current 2a/div 200s/div v in = 5v en v out lx1 voltage v in = 3.3v pg1 en v out lx1 voltage v in = 3.3v pg1 en v out lx1 voltage v in = 3.3v pg1
isl78236 17 fn8624.0 april 28, 2014 submit document feedback figure 47. current share balancing, 0a to 6a figure 48. current shar e balancing, 2a to 6a typical performance for current sharing pwm operation unless otherwise noted, operating conditions are: t a = +25c; v out = 1.8v, i out1 +i out2 = 0a to 6a, l1 = l2 = 0.6h, c out = 4x22f, f sw = 2.5mhz. il2 1a/div il2 1a/div v in = 5v load ramp = 6a/ms il2 1a/div il2 1a/div v in = 5v load ramp = 6a/ms
isl78236 18 fn8624.0 april 28, 2014 submit document feedback theory of operation the isl78236 is a dual 3a or sing le current sharing 6a step-down switching regulator optimized for low output ripple point-of-load power in automotive applications. the regulator operates at 2.5mhz internally fixed switching frequency allowing small output filter components while maintaining up to 95% efficiency. the two channels are 180 out-of-phase operation to reduce input ripple currents and emi. the supply current is typically only 8a when the regulator is shutdown. pwm control scheme pulling the sync pin hi (>1.5v) forc es the converter into pwm mode in the next switching cycle regardle ss of output current. each of the channels of the isl78236 employ the current-mode pulse-width modulation (pwm) control scheme for fast transient response and pulse-by-pulse current limiting, as shown in the ? block diagram ? on page 5 with waveforms in figure 49 . the current loop consists of the oscillator, the pwm comp comp arator, current sensing circuit, and the slope compensation for the current loop stability. the current sensing circuit consists of the resistance of the p-channel mosfet when it is turned on and the current sense amplifier csa. the gain for the current sensing circuit is typically 0.2v/a. the control reference for the current loops comes from the error amplifier, eamp, of the voltage loop. the pwm operation is initialized by the clock from the oscillator. the p-channel mosfet is turned on at the beginning of a pwm cycle and the current in the mosfet starts to ramp up. when the sum of the current amplifier csa1 (or csa2 on channel 2) and the compensation slope (0.46v/s) re aches the control reference of the current loop, the pwm comp comparator sends a signal to the pwm logic to turn off the p-mosfet and to turn on the n-channel mosfet. the n-mosfet stays on until the end of the pwm cycle. figure 49 shows the typical operating waveforms during the pwm operation. the dotted lines illustra te the sum of the compensation ramp and the current-sens e amplifier csa_ output. the output voltage is regulated by controlling the reference voltage to the current loop. the bandgap circuit outputs a 0.8v reference voltage to the voltage control loop. the feedback voltage signal comes from the fb pin. the soft-start block only affects the operation during the start-up and will be discussed separately. the error amplifier is a transconductance amplifier that converts the voltage error signal to a current output. the voltage loop is internally compensated with the 27pf and 390k rc network. the maximum eamp voltage output is precisely clamped to the bandgap voltage (1.172v). synchronization control the synchronization frequency can be operated to a range of 6mhz to 8mhz by an external signal applied to the sync pin. the sync pin has logic threshold levels of 0.4v and 1.5v for low and high respectively, to allow for external clock signals to be of different magnitude regardless of supply voltage to isl78236. the 1st falling edge on the sync triggers the rising edge of the pwm on pulse of channel 1. the 2nd falling edge of the sync triggers the rising edge of the pwm on pulse of channel 2. typically, the pulse width of the sync signal should be 50% duty cycle, however, it is recommended that the pulse width be in the range of 50ns to 100ns for valid synchronization. this process alternates indefinitely allowing 180 output phase operation between the two channels. it is important to note that this operation makes the switching frequency of each channel 1/2 of the sync frequency. thus, channel 1 and channel 2 have a synchronized switching freq uency of 3mhz to 4mhz. output current sharing the isl78236 dual outputs ar e paralleled for multi-phase operation in order to support 6a output. channel 1 and channel 2 switches 180 out-of-phase to reduce input ripple currents. in parallel configuration, external so ft-start should be used to ensure proper full loading start-up. connect the fbx pins together and connect a soft-start capacitor from ss pin to gnd. external compensation using the comp pin is required for current sharing operation. please see table 2 for recommended values in current sharing mode. the current sharing balancing is dependent on the current sense amplifie r matching between the two channels. the matching is internally trimmed and provides excellent balancing of output currents. see figures 47 and 48 for typical output current matching. overcurrent protection csa1 and csa2 are used to monitor output 1 and output 2 channels respectively. the overcurrent protection is realized by monitoring the csa output with the ocp threshold logic, as shown in the ? block diagram ? on page 5 . the current sensing circuit has a gain of 0.2v/a, from the p-mosfet current to the csa output. when the csa output reaches the threshold, the ocp comparator is tripped to turn off the p-mosfet immediately. the overcurrent function protects the switching converter from a shorted output by monitoring the current flowing through the upper mosfets. upon detection of overcurrent co ndition, the upper mosfet will be immediately turned off and w ill not be turned on again until the next switching cycle. upon de tection of the initial overcurrent condition, the overcurrent fault counter is set to 1 and the overcurrent condition flag is set from low to high. if, on the subsequent cycle, another overcu rrent condition is detected, the oc fault counter will be incremented. if there are 17 sequential oc fault detections, the regulato r will be shut down under an overcurrent fault condition. an overcurrent fault condition will result with the regulator attempting to restart in a hiccup mode with the delay between restarts being 8 soft-start periods. at the figure 49. pwm operation waveforms v eamp v csa1 duty cycle i l v out
isl78236 19 fn8624.0 april 28, 2014 submit document feedback end of the eighth soft-start wait period, the fault counters are reset and soft-start is attempted again. if the overcurrent condition goes away prior to the oc fault counter reaching a count of four, the overcurrent cond ition flag will set back to low. the isl78236 also features current sense amplifiers on the n-mosfet for negative overcurrent protection. if the negative output current reaches -2.5a, the part enters negative ocp. at this point, all switching stops an d the part enters tri-state mode while the pull-down fet is discharg ing the output until it reaches normal regulation voltage, then the ic restarts. power-good (pg) there are two independent power-good signals. pg1 monitors the output channel 1 and pg2 monitors the output channel 2. when powering up, the open-col lector power-good output holds low for about 1ms after the output reaches within 8% of the preset output voltage. the pg pin will pull low under fault conditions when an overcurrent, otp or uvlo event occurs. uvlo when the input voltage is below the undervoltage lockout (uvlo) threshold (2.85v max), the regulator is disabled and the pg pin will pull low. enable the enable (enx) inputs allows th e user to control the turning on or off each channel of the regulator for purposes such as low power shutdown or power-up sequencing. when the regulator is enabled, there is typically a 600s delay for waking up the bandgap reference, afterwards the soft start-up sequence begins. soft start-up the soft-start-up eliminates the in-rush current during the start-up. the soft-start block outputs a ramp reference to both the voltage loop and the current loop. the two ramps limit the inductor current rising speed as well as the output voltage speed so that the output voltage rises in a controlled fashion. when the fb voltage is less than 0.2v, the pwm operating frequency is 1/2 of the normal frequency. when the ss soft-start pin is tied to the vin pin, the soft start-up time is internally set to 1.5ms. this internal soft-start mode is only for dual output operation. in current sharing mode, for externally programmable soft-start time, connect a capacitor from the ss pin to gnd. a 5a current source charges up the soft-start capacitor and sets the soft-start ramp time. the soft-start capacitor, c ss , should not be larger than 33nf. see equation 2 for calculating the soft-start ramp time. it is recommended to operate the internal soft-start ramp time only in dual output mode. in current share mode external soft-start should be used. discharge mode (soft-stop) when a transition to shutdown mode occurs, or the input uvlo fault latch is set, the lx pin discharges to pgnd through an internal 100 ? switch. power mosfets the integrated high-side and low-side power mosfets are optimized for best efficiency while delivering up to 3a current. the on-resistance for the p-mosfet is typically 50m ? and the on-resistance for the n-mosfet is typical 50m ? . 100% duty cycle the isl78236 features 100% duty cycle operation to maximize the battery life in portable applic ations. when the battery voltage drops to a level that the isl78236 can no longer maintain the regulation at the output, the re gulator completely turns on the p-mosfet. the maximum dropout voltage under the 100% duty cycle operation is the product of the load current and the on-resistance of the p-mosfet. thermal shutdown the isl78236 has built-in thermal protection. when the internal temperature reaches +150c, the regulator is completely shut down. as the temperature drops to +125c, the isl78236 resumes operation by stepping through a soft start-up. applications information output inductor and capacitor selection to consider steady state and transient operation, isl78236 typically uses a 0.6h output inductor. higher or lower inductor value can be used to optimize the total converter system performance. for example applic ations with output voltage >3.3v, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value can be increased. the inductor ripple current can be expressed in equation 3 : the inductor?s saturation current rating needs to be larger than the peak current. the isl78236 ov ercurrent protection threshold is typically 4.8a. the saturation current needs to be over 4.8a for maximum output current application. t ss s ?? c ss ? f ?? 6.25 ---------------------- - = (eq. 2) ? i v o 1 v o v in --------- ? ?? ?? ?? ? lf s ? -------------------------------------- - = (eq. 3)
isl78236 20 fn8624.0 april 28, 2014 submit document feedback isl78236 uses an internal compensation network and the output capacitor value is dependent on the output voltage. the ceramic capacitor is recommended to be x5r or x7r. the recommended minimum output capacitor values for the isl78236 are shown in table 3 . in table 3 , the minimum output capacitor value is given for different output voltages to make sure the converter system is stable. while ceramic capacitors offer excellent overall performance and reliability, the actual in-circuit capacitance must be considered. ceramic capacitors are rated using large peak-to-peak voltage swings and with no dc bias. in the dc/dc converter application, these conditio ns do not reflect reality. as a result, the actual capacitance ma y be considerably lower than the advertised value. consult the manufacturers data sheet to determine the actual in-application capacitance. most manufacturers publish capacitance vs dc bias so that this effect can be easily accommodated. the effects of ac voltage are not frequently published, but an assumption of ~20% further reduction will generally suffice. the result of these considerations may mean an ef fective capacitance 50% lower than nominal and this value should be used in all design calculations. nonetheless, ceramic capacitors are a very good choice in many applications due to their reliability and extremely low esr. equations 4 and 5 allow calculation of the required capacitance to meet a desired ripple voltage level. additional capacitance may be used. for the ceramic capacitors (low esr): where ? i is the inductor?s peak-to-peak ripple current, f sw is the switching frequency and c out is the output capacitor. if using electrolytic capacitors then: output voltage selection the output voltage of the regula tor can be programmed via an external resistor divider, which is used to scale the output voltage relative to the internal reference voltage and feed it back to the inverting input of the error amplifier. refer to figures 3 and 4 . the output voltage programming resistor, r 2 (or r 5 in channel 2), will depend on the desired output voltage of the regulator. the value for the feedback resistor is typically between 50k ? and 312.5k ? . setting r 2 and v out , r 3 will be: for better performance, add 12pf in parallel with r 2 (or r 5 ) for faster transient response ?? minimum output voltage the isl78236 switching frequency f s (2.5mhz typical, 2.85mhz max) and the minimum lx pin on time (140ns, max) sets a minimum duty cycle of the converter under worst case scenario of 0.4 across temperature. because of this minimum duty cycle, there is an input v in to output v out range the isl78236 is capable of regulating to. the ratio of output to input (v out /v in ) must be higher than 0.4 to maintain output voltage regulation. for example, it is no t recommended to regulate below 2.0v for v in = 5v and below 1.2v for v in = 3v as the minimum duty cycle limitation will impact output voltage. note that when external synchronization is us ed, the switching frequency is higher than 2.85mhz which further restricts the v out /v in range of operation. input capacitor selection the main functions for the input capacitor are to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current flowing back to the battery rail. one 22f x5r or x7r ceramic capacitor is a good starting point for the input capacitor selection per channel. loop compensation design when a soft-start capacitor is connected to the ss pin, the comp pin is active for external loop compensation. the isl78236 uses constant frequency peak current mode control architecture to achieve a fast loop transient response. an accurate current sensing pilot device in parallel with the upper mosfet is used for peak current control signal an d overcurrent protection. the inductor is not considered as a state variable since its peak current is constant, and the system becomes a single order system. it is much easier to design a type ii compensator to stabilize the loop than to implem ent voltage mode control. peak current mode control has an inherent input voltage feed-forward function to achieve go od line regulation. figure 50 shows the small signal model of the synchronous buck regulator. table 3. minimum output capacitor value vs v out v out (v) c out (f) l (h) 1.2 2 x 22 0.5~1.1 1.6 2 x 22 0.5~1.1 1.8 2 x 22 0.5~1.68 2.5 2 x 22 0.5~1.68 3.3 2 x 6.8 0.5~2.2 3.6 10 0.5~2.2 v outripple ? i 8 ? f sw ? c out -------------------------------------- - = (eq. 4) v outripple ? i*esr = (eq. 5) r 3 r 2 x0.8v v out 0.8v ? ---------------------------------- = (eq. 6)
isl78236 21 fn8624.0 april 28, 2014 submit document feedback figure 51 shows the type ii compensator and its transfer function is expressed, as shown in equation 7 : where , compensator design goal: high dc gain choose loop bandwidth f c 100khz or below gain margin: >10db phase margin: >40 the compensator design procedure is as follows: the loop gain at crossover frequency of f c has a unity gain. therefore, the compensator resistance r 6 is determined by equation 8. where r t is the current sense amplifier gain (0.2v/a) and gm is the trans-conductance, g m , of the voltage error amplifier in each phase (see ?electrical specification? table for ? error amplifier trans-conductance ? on page 8 ). compensator capacitor c 6 and c 7 is then given by equation 9 . an optional zero can boost the phase margin. ? cz2 is a zero due to r 2 and c 3 ? example: v in = 5v, v o = 1.8v, i o = 3a, fs = 2.5mhz, r 2 =124k ? , r 3 = 100k ? , c o =2x22f/3m , l = 0.6h, f c = 100khz, then compensator resistance r 6 : use a standard 124k 1% tolerance or better resistor. use the closest standard values for c 6 and c 7 . there is approximately 2pf parasitic capacitance from v comp to gnd; therefore, c 7 is optional. use c 6 = 220pf and c 7 = open. use c 3 = 22pf. note that c 3 may increase the loop bandwidth from previous estimated value. pcb layout recommendation the pcb layout is a very important converter design step to make sure the designed converter works well. for isl78236, the power loop is composed of the output in ductor l?s, the output capacitor c out1 and c out2 , the lx?s pins, and the pgnd pin. it is necessary to make the power loop as small as possible and the connecting traces among them should be direct, shor t and wide. the switching node of the converter, the lx pins, and the traces connected to the node are very noisy, so keep the voltage feedback trace away from these noisy traces. the fb network should be as close as possible to its fb pin. sgnd should have one single connection to pgnd. the input capacitor should be placed as closely as possible to the vin pin. also, the ground of the input and output capacitors should be connected as closely as possible. the heat of the ic is mainly dissipated through the thermal pad. maximizing the copper area connected to the thermal pad is preferable. in addition, a solid ground plane is helpful for better emi performance. it is recommended to add at least 5 vias ground connection within the pad for the best thermal relief. d v in d i l in in i + 1:d + l i co rc -av(s) d comp v r t fm he(s) + t i (s) k o v t v (s) i l p + 1:d + rc ro -av(s) r t fm he(s) t i (s) k o t(s) ^ ^ v ^ ^ ^ ^ ^ ^ figure 50. small signal mo del of synchronous buck regulator r lp gain (vloop (s(fi)) - + r 6 v v v o gm v c 7 - + c 6 v ref v fb v comp figure 51. type ii compensator c 3 r 2 r 3 a v s ?? v ? comp v ? fb ------------------- - gm r 3 ? c 6 c 7 + ?? r 2 r 3 + ?? ? -------------------------------------------------------- 1 s ? cz1 ------------ - + ?? ?? 1 s ? cz2 ------------ - + ?? ?? s1 s ? cp1 ------------- + ?? ?? 1 s ? cp2 ------------- + ?? ?? -------------------------------------------------------------- - = = (eq. 7) ? cz1 1 r 6 c 6 -------------- - ? cz2 1 r 2 c 3 -------------- - = ? cp1 ? c 6 c 7 + r 6 c 6 c 7 ---------------------- - ? cp2 r 2 r 3 + c 3 r 2 r 3 ---------------------- - = ? = , = r 6 2 ? f c v o c o r t gm v fb ? --------------------------------- - 15.7 3 ? 10 f c v o c o ? == (eq. 8) c 6 r o c o r 6 -------------- - v o c o i o r 6 -------------- - c 7 max of r c c o r 6 -------------- - 1 ? f s r 6 --------------- - (, ) = , = = (eq. 9) c 3 1 ? f c r 2 --------------- - = (eq. 10) r 6 15.7 3 ? 10 100khz 1.8v 44 ? f ? ? ? 124k ? == (eq. 11) c 6 1.8v 44 ?? f 3a 124k ? ? ------------------------------- - 213pf = = (eq. 12) c 7 max 3m ? 44 ? f ? 124k ? -------------------------------- - 1 ? 2.5mhz 124k ? ?? ---------------------------------------------------- (, ) 1pf 1pf (,) = = (eq. 13) c 3 1 ? 100khz 124k ? ?? ---------------------------------------------------- = 26pf = (eq. 14)
isl78236 22 fn8624.0 april 28, 2014 submit document feedback thermal performance delivering a full load output cu rrent of 6a across the ambient operating temperature is strongly dependent on the thermal characteristic of the pcb layout. the power dissipation of the ic and the thermal impedance of the board will result in a temperature gradient between ambient and junction. power dissipation curves for typical application can be found in figures 7 and 8 for dual output operation and figures 37 and 38 for current sharing operation. if the junction temperature exceeds the +150c over-temperatu re protection threshold the regulator will be disabled. the theta ja ( ? ja ) spec shown in the ? thermal information ? on page 8 is based upon jedec standard jesd51-5. however, real world application boards will differ from the jedec standard thus producing different theta ja results. for example, the jesd51-5 specifies the thermal attach pad via only to the top buried layer. most practical applications will have the via connect to all layers of the pcb board ground plane. jesd51-5 also requires that buried planes use 1 oz. copper while the outer planes use 2 oz. copper. it is recommended to have 2 oz. or greater copper on all layers in application boards. it is essential to have the package thermal pad connected to a top layer pcb ground pad with th e via connecting to additional ground planes. this is where most of the thermal relief will occur. the four pgnd pins of the isl78236 should be connected to the thermal pad also. these connections provide the extra thermal relief to mini mize theta ja allowing the isl78236 to maintain full output current up to +105c. see figure 52 for an example layout of the thermal relief pad. figure 52. recommended thermal pad layout pin 1 lx2 pgnd2 pgnd2 pgnd1 pgnd1 lx1 comp nc fb1 sgnd pg1 sync lx2 vin2 vin2 en2 pg2 fb2 lx1 vin1 vin1 vdd ss en1 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 789101112 25 pad
isl78236 23 intersil automotive qualified products are manufactured, asse mbled and tested utilizing ts16949 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8624.0 april 28, 2014 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change april 28, 2014 fn8624.0 initial release.
isl78236 24 fn8624.0 april 28, 2014 submit document feedback package outline drawing l24.4x4d 24 lead quad flat no-lead plastic package rev 3, 11/13 0 . 90 0 . 1 5 c 0 . 2 ref typical recommended land pattern 0 . 05 max. ( 24x 0 . 6 ) detail "x" ( 24x 0 . 25 ) 0 . 00 min. ( 20x 0 . 5 ) ( 2 . 50 ) side view ( 3 . 8 typ ) base plane 4 top view bottom view 7 12 24x 0 . 4 0 . 1 13 4.00 pin 1 18 index area 24 19 4.00 2.5 0.50 20x 4x see detail "x" - 0 . 05 + 0 . 07 24x 0 . 23 2.45 (+ 0.10mm) pin #1 corner (c 0 . 25) 1 seating plane 0.08 c 0.10 c c 0.10 m c a b a b (4x) 0.15 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: (- 0.15mm)

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